Method of Auto : matic Fault - Detection Test Generation

ro determine whether an integrated digital circuit is working properly, one may apply to the circuit a set of· well-devised test sequences and compare the resultant outputs with the corresponding correct outputs. Any discrepancies indicate the presence of a fault. The main task here is to find a set of test sequences which can detect the presence of any prescribed fault in the circuit. This test generation problem will become formidable for large scale integrated arrays, since large number of logic circuits may be contained in an array with a limited number of exterior terminals. Presently, the approach most commonly used in test generation is computer fault simulation. In other words, data are repetitively processed through a cycle of two steps, i.e., test generation followed by test verification. In each cycle, the generation of primary output test sequences can be accomplished by a computer logic simulation technique. The primary-input test sequences are manually generated by engineers because much creative work is involved. In this paper, a method will be proposed to generate primary-input test sequences for 4-phase MOS sequential switching circuits. This method can find the shortest primary-input test sequences to detect a given fault on an array. An MOS transistor stuck at either short or open permanently is the failure mode to be considered. A single fault assumption4 will be made in this paper.